1. Technical Field
The present invention relates in general to integrated circuit chips having a voltage regulator as an on-chip power supply and, more particularly, to a latch-up protection circuit which prevents damage to a CMOS integrated circuit chip due to transient surges or internal-circuitry initiated latch-ups and which interrupts and clears any latch-up condition or SCR mode.
2. Background Art
As is well known, in the conventional fabrication of integrated circuits, an epitaxial layer doped with one ion type is grown on the surface of a substrate doped with a second ion type and then various impurities are diffused into the epitaxial layer to create the requisite elements (e.g., gate, channel, etc.) of the desired electronic device. The diffusion process, in addition to forming the desired electronic device, can also create what is known in the art as a parasitic transistor which may exist between a diffusion region, the epitaxial layer and the substrate. When a CMOS inverter stage is formed, a pair of parasitic transistors are formed which have the configuration of a silicon controlled rectifier (SCR) circuit.
The parasitic transistors remain inactive during the normal operation of the integrated circuit and therefore generally do not have an effect. However, a transient surge or electrostatic discharge may change the relative electrical characteristics of one or more of the diffusion regions enough so that the regions which comprise the parasitic SCR circuit become conductive and current passes through portions of the various layers of the integrated circuit unintended for such current flow. Such a phenomenon is referred to as "latch-up" condition). The latch-up condition can be especially destructive to CMOS integrated circuits, since they and their associated components are designed to normally draw small quantities of current. An integrated circuit may be cleared of the latch-up condition by reducing the input voltage or current below the sustaining voltage or sustaining current, respectively, the value of which may vary according to the integrated circuit experiencing the condition.
When a latch-up condition occurs, the integrated circuit appears as a very low impedance across the output of a voltage regulator which may be used to drive the integrated circuit. Thus, it not only becomes necessary to limit the current input tot he integrated circuit for protection, but also to clear the integrated circuit of the latch-up condition so that the voltage regulator and the integrated circuit may again function properly.
CMOS technology has strived to develop processing features which result in greater degrees of latch-up immunity. Features such as guard rings, epi wafers, N-well spacing restrictions, retrograde N-well, and TiSi junctions have each been used to improve the latch-up resistance of today's CMOS technology. Unfortunately, present processing enhancements do not provide complete latch-up immunity. Only if the latch-up hold voltage is greater than the chip power supply voltage can a chip be considered latch-up free. Maintaining such a condition, however, is not always realistic given layout and design constraints.
The general principal of any latch-up protection circuit is to interrupt the latch-up current before damage occurs to the integrated circuit chip. Latch-up current generally flows from an external power supply to ground and its interruption requires removing (or lowering) the external power supply voltage or isolating the external supply from the on-chip power supply by means of a switching device. Such a switching approach is described in U.S. Pat. No. 4,594,633, issued to Townsend et al. and entitled "Integrated Circuit Protection Circuit ". Briefly, this circuit comprises a "crow bar" type of circuit which responds to an over current condition to the load by adding a short circuit across the load. A predetermined time after the latch-up condition is detected, normal operation is automatically restored. However, there is no open circuiting to reset the latch-up condition. Further, adding a power switching device solely for the purpose of preventing latch-up is often undesirable because of the cost involved.
Recent progresses in CMOS technology have necessitated a lower internal power supply voltage than the conventional five volt external power supply due to reliability concerns of the shorter channeled CMOS devices. Integrated circuit chips which utilize an on chip voltage regulator to provide this lower chip voltage from a higher external voltage supply present a unique opportunity for latch-up protection circuitry. Since all the chip current is channeled through the voltage regulator, except for a few biasing circuits consuming a few tens of micro amps, the possibility exists to introduce a circuit which interrupts the flow of current within the voltage regulator after the detection of a latch-up condition within the integrated circuit chip. The present invention is directed to implementation of such a unique approach.